1. Field of the Invention
The present invention relates to a field emission display device, and more particularly relates to a field emission display device that is able to achieve a high-luminance display panel with high aperture ratio and large-size fabricating capability.
2. Information Disclosure Statement
A field emission display device generally represents a device in which a field emission device is applied to a flat panel display device. This kind of field emission display device is produced by vacuum packaging a lower plate having a field emitter array and an upper plate having a phosphor, in parallel with narrow gap (within 2 mm), and it displays an image by the cathode luminescence of the phosphor caused by bombarding electrons that are emitted from the field emitters of the lower plate into the phosphor of the upper plate. Recently, it is widely researched and developed as a substitutional flat panel display for the conventional cathode ray tube (CRT).
A field emission display device is classified into a simple matrix type panel and an active matrix type panel according to the structure of the pixels arranged in matrix on the lower plate. In case of a simple matrix type panel each pixel comprises only a field emitter arrays, whereas of an active matrix type panel each pixel comprises a field emitter arrays and semiconductor devices (mainly, transistors) that controls field emission currents of the field emitter array. A prior active matrix type panel is illustrated in FIG. 1 and FIG. 2.
FIG. 1 is an overall schematic diagram illustrating a lower plate structure of a prior field emission display device. Each pixel formed on a single crystal silicon wafer 10P comprises a field emitter array 20P comprising a plurality of triode-type field emitters, a control transistor 30P having a drain connected to the emitter electrode of the field emitter array 20P, a memory capacitor 40P having an upper electrode connected to the gate electrode of the control transistor 30P, and an addressing transistor 50P having a drain connected to the upper electrode of the memory capacitor 40P. The addressing transistor 50P writes scan signals and data signals from a signal line of a display into each pixel, the memory capacitor 40P stores the data signals of a display, and the control transistor 30P controls field emission currents of the field emitter array 20P according to the data signals.
A detailed structure of the pixel is illustrated in FIG. 2.
In a prior active matrix field emission display device, a pixel, which compose a lower plate, comprises; a p-type silicon wafer 10P, an addressing transistor 50P comprising a source 501P/drain 502P, made of n-type silicon, formed on said wafer 10P, a gate 504P formed on the upper part of the wafer 10P, a source electrode 505P formed on the upper part of the wafer 10P and electrically connected to the source 501P, and a gate insulation film 503P to electrically insulate the gate 504P from the source 501P/drain 502P and silicon channel 10P, a memory capacitor 40P comprising a lower electrode 401P, formed on the wafer 10P, made of n-type silicon, an upper electrode 403P, formed on the upper part of the wafer 10P, make of metal or n-type silicon, and a gate dielectric film 402P between the lower electrode 401P and the upper electrode 403P, a control transistor 30P comprising a source 301P/drain 302P, formed on the wafer 10P, made of n-type silicon, a gate 304P formed on the upper part of the wafer 10P, a source electrode 305P formed on the upper part of the wafer 10P and electrically connected to the source 301P, and a gate insulation film 303P to electrically insulate the gate 304P from the source 301P/drain 302P and silicon channel 10P, a field emitter array 20P comprising a plurality of field emitter tips 201P formed on the drain 302P of the control transistor 30P and a gate 202P, and a connection electrode 345P connected to drain 502P of the addressing transistor 50P, an upper electrode 403P of the memory capacitor 40P, and a gate electrode 304P of the control transistor 30P.
The display device is operated by applying a prescribed voltage required for a field emission to the gate 202P of the field emitter array 20P, thereafter writing a scan and a data signal of a display to the gate 504P and the source 501P of the addressing transistor 50P. Once the signal is written, it is stored in the memory capacitor 40P and continuously operates the control transistor 30P until the next scan signal arrives (In other words, the control transistor 30P is being operated continuously even in non-scan interval.). Therefore, it is accomplished to largely increase the average emission current of a given field emitter array, thereby largely increase the brightness of a display.
The lower plate of a prior field emission display device, by the benefit of using a single crystal silicon wafer 10P, can produce a high-performance addressing transistor 50P, memory capacitor 40P and control transistor 30P, thereby easily produce a high performance active matrix field emission display device. However, it can not produce a large size display device because of the high price of a single crystal silicon wafer 10P and the limit of the size thereof. And the vacuum packaging is difficult because of the mechanical weakness of a single crystal silicon wafer 10P.
In addition, the lower plate of a prior field emission display device has a good data signal holding performance because it has an independent memory capacitor 40P in each pixel, however, it has the demerits that is needs additional processes for the fabrication of the memory capacitor 40P and an aperture ratio of a pixel is decreased because of the area reduction by the memory capacitor 40P existence.